Against a background of steadily increasing processor operating speed in computers, such as personal computers, workstations, and servers, it is essential that the operating speed of semiconductor memories is increased to prevent performance losses. Thus, in the last few years, memory modules have been developed with high-speed and high-density memory blocks, such as DDR-DRAMs (Double Data Rate Dynamic Random Access Memory) of the generation stages 1, 2 and 3 in which it was possible to improve the operating speed and structural density.
In a conventional DIMM semiconductor memory module with DDR-DRAMs as semiconductor memory chips, two or four ranks per semiconductor memory module are provided, for example, where one rank each may be arranged on the front or, respectively, the rear side of the semiconductor memory module, or two (2) ranks each may be arranged in stacks on one same side of the semiconductor module, respectively. According to common definition, “rank” is understood as the number of semiconductor memory chips (DRAMs) necessary to occupy the complete bit width of a signal bus connecting the semiconductor memory units with a memory controller. Accordingly, with a bus width of 64 bit or, respectively, 72 bits including an error correction block ECC (Error Correction Code), 16 (or, respectively, 18 with ECC) semiconductor memory chips are required per rank with 4 bit data width or 8 (respectively, 9 with ECC) semiconductor storage chips with 8 bit data width. For example, 4 ranks with 8 bit wide memory units each are realized in registered DIMMs in which the control and address bus is buffered. More precisely, on an x8 based DIMM with 4 ranks on the front and rear side of the wiring board, two ranks each of 8 memory blocks each are wired to each other at several wiring levels by vias and signal wiring runs passing through the wiring board.
In a conventional memory chip topology, for example, in DDR3 DRAMs, the individual memory chips are connected by a flyby topology with the memory controller. The control and address signal pins of the individual memory chips are each connected in series to a flyby bus.
A major disadvantage of the flyby topology is the too narrow bandwidth for high data rates of 1.6 Gbit/s/pin, for example, and a too low structural density. An improved semiconductor memory array by which a wide bandwidth and a high structural density can be realized even at high data rates of at least 1.6 Gbit/s/pin is desirable.